There have been various attempts to produce a low on-state resistance (RON) semiconductor device. In the case of a trench metal oxide semiconductor field effect transistors (MOSFETs), the on-state resistance (RON) may be lowered by reducing an interval between two adjoining trenches, which is known as cell pitch. An example of a trench MOSFET is shown in FIG. 1. A trench MOSFET having a reduced cell pitch may be constructed by, for example, vertically forming an N source type and a P type body region in the same mesa, which can eliminate need for a separate contact region and hence allow for reduction in cell pitch. This approach, however, may not render the trench structure operable as a normal MOSFET. More specifically, a source region formed in a mesa needs to be sufficiently large to carry out normal MOSFET operations. If the cell pitch is reduced too much, there may not be sufficient space to form an adequately sized source region. Therefore, there is a limit to reducing cell pitch, and the fully reduced cell pitch without rendering other components inoperable may not be sufficient for substantially lowering the on-state resistance (RON).
Accordingly, there is a need for an optimized semiconductor device structure for lowering an on-state resistance (RON), and a manufacturing method thereof.